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According to the trend of device scaling, a gate dielectric layer for a metal-oxide-semiconductor (MOS) transistor needs to be made as thin as possible so as to maintain sufficient capacitance between the gate electrode and the channel. However, such a thin gate dielectric layer is readily damaged by etching, plasma etching or reactive-ion etching in the process of forming shallow trench isolation regions. The formation of shallow trench isolation regions to define a field region for a 0b46394aab
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